(1) Field of the Invention
The present invention relates to methods used for fabrication of metal oxide semiconductor filed effect transistors, (MOSFET), devices, and more specifically to a process used to create a polycide gate structure, on a thin gate insulator layer.
(2) Description of Prior Art
The semiconductor industry is continually striving to improve the performance of semiconductor devices while still attempting to decrease the cost of semiconductor chips. These objectives have been successfully addressed via the use of micro-miniaturization, or the use of sub-micron features, in semiconductor devices. Smaller features reduce performance degrading capacitances and resistances, resulting in faster devices. The use of smaller features also allow smaller chips to be fabricated, still possessing the same level of integration as counterparts with larger features, and thus allowing more, smaller, chips to be realized from a starting wafer, thus reducing the processing costs for a specific chip.
Micro-miniaturization has been realized by advances in specific semiconductor fabrication disciplines, such as photolithography and dry etching. The use of more sophisticated exposure cameras, as well as the use of more sensitive photoresist materials, have allowed sub-micron features to be routinely obtained in photoresist layers. In addition the use of advanced dry etching tools and processes, have allowed the sub-micron images in photoresist layers, to be successfully transferred to underlying materials used in the fabrication of advanced semiconductor devices. However when attempting to use micro-miniaturization to fabricate advanced semiconductor devices, for example using narrow polycide, (metal silicide-polysilicon), gate structure, on very thin gate oxide layers, special care must be used in order to avoid problems associated with the smaller device features. For example during the definition of a narrow polycide gate structure, via the use of anisotropic dry etching procedures, micro-trenches can be created at the foot, or edges, of the narrow polycide gate structure, during the patterning of the polysilicon layer, which underlies the metal silicide layer of the polycide structure. The trenching phenomena, more pronounced with narrower features, can lead to yield loss resulting from polysilicon gate to substrate leakages or shorts. In addition to severe over etch of the polysilicon, in the polycide gate structure occurs, etch pits can also be formed in the subsequent source and drain region, again possibly adversely influencing device yield. If the selectivity of the polysilicon etch procedure is increased to decrease the occurrence of trenching or pitting, the profile of the polycide gate structure can be tapered, thus adversely influencing yield and performance.
This invention will offer a process for forming polycide gate structures, in which trenching and pitting phenomena are avoided by terminating the polysilicon etch procedure, prior to exposure of the underlying gate oxide layer. With about 100 to 200 Angstroms of polysilicon remaining in subsequent source and drain regions, the etch procedure is terminated. The lightly doped source and drain region, (LDD), is implanted through the very thin residual polysilicon layer, into the underlying substrate. An oxidation procedure, used to create a sidewall insulator layer for the polycide gate structure, results in the oxidation of the residual polysilicon, on the LDD region, subsequently removed during the formation of an insulator spacer, on the sides of the polycide gate structure. Prior art, such as an invention offered by Kamijo, et al, in U.S. Pat. No. 5,032,535, describe a process in which a partial dry etching procedure, for a polysilicon gate structure, is used. However their process is completed with additional dry etching, thus being exposed to the trenching and pitting phenomena. Our invention features the use of oxidation to complete the formation of the polysilicon portion of the polycide gate structure.